The Die Cap project will attempt to combine the advantages of chip-on-board technology with some of the conveniences associated with packaged parts, to improve the reliability of memory stacks and to reduce their footprint. To make this product available to future flight programs, the design, construction and test of the part will be managed in a way that makes the final product commercially viable and easy to specify and procure.
Efforts to miniaturize flight electronics have resulted in new and interesting packaging and handling techniques for integrated circuit (IC) die. A recent success in miniaturization which is being used here at NASA GSFC, is stacked dice technology. Using this technique, the footprint for 80 Mbytes of memory is reduced by a factor of 20. The architecture of the stack also improves performance characteristics associated with reduced current path lengths. The driving need for more memory and more efficient system performance has caused several GSFC projects to design memory stacks into their flight electronics, namely HST, MAP and EO1. Bare stacks, without the multichip module package, are being designed into Johns Hopkins University Applied Physics Laboratory’s standard flight computer and data handling assembly which will be fabricated using almost entirely chip-on-board technology (IC die mounted directly to the circuit board).
A significant problem emerged as wire bond failures occurred during qualification vibration testing of the HST memory stack modules. Electrical connection between the stacks and the module package is accomplished via standard gold bond wires. Due to the height of the stacks and their position in the package, the wires and the bonds took on a slightly different physical configuration than that normally found in electronic packaging; the ball and crescent bond locations were switched, the wire was fairly long and it was nearly vertical with respect to the package floor. The vibration failures were evidence of a bonding process that was not well controlled. More importantly, the relatively long length of the bond wire presents a mass load to the bond during shock conditions that can break the bond. This problem has yet to be resolved while projects continue to rely on memory stacks, to meet size constraints. This proposal presents a solution for this problem as well as a robust technology that can be applied to any stacked IC.
2.0 DIE CAP Pending PatentIn May of 1996, Case No. GSC 13,857-1 was assigned to a Disclosure of Invention for the DIE CAP. The patent application describes the technology as "an effective means of interfacing electronic dice to a mounting substrate [which] allows for the use of increased packaging densities as well as allowing pre-testing of electronic devices prior to assembly." It notes the advantage of this technique over competing technologies such as flip-chip, since it provides a device which can be considered "known good", fully tested and guaranteed by the manufacturer, and can be inspected for good solder joints. The construction is described as "a block of either aluminum nitride or ceramic material which has been manufactured to allow the mounting of solder bumped die onto its mounting surface to pads which are connected to metallized castellations around the periphery of the die cap." (See Figure 1). This construction allows the use of existing electronic packaging materials and technologies to adapt the die stack with test sockets and surface mounting equipment. It further states that this technology is suitable for a wide range of commercial, military and space products which rely on high density electronic packaging.
3.0 Goal and Objectives
The goal of the Die Cap project is to develop a die level package, with a die stack manufacturer, that will make die stacks fully testable, using existing fixturing and integration techniques. The Die Cap/memory stack assembly is intended to be a drop-in replacement for the wire bonded types. The objective is to use NASA GSFC’s Die Cap concept to fabricate prototypes that will be tested and integrated on boards in flight configuration and validated for mechanical and electrical viability.
Figure 1. Die Cap
4.0 Development Approach
Irvine Sensors, a die stack manufacturer, has expressed an interest in the Die Cap technology. This task would initiate a prototype build using Irvine Sensor die stacks. Irvine and GSFC will combine efforts to establish test sockets and boards for the finished parts. Irvine will be asked to do full military level lot acceptance testing, in order to deliver "known good" parts. GSFC will run mechanical and thermal tests to validate the assembly and to identify any material problems associated with differing coefficients of thermal expansion. A finite element analysis is recommended to establish mechanical design limits associated with vibration and thermal stress.
Swales Aerospace will be participating as a partner investigator and a student from the Space Academy has been assigned through the DDF program.
5.0 Industry SourcesThe following companies have been identified as possible sources for materials and engineering services required for completion of this project.
Aluminum Nitride Cofired Ceramic Substrate Suppliers:NTK Technical Ceramics, Santa Clara, CA 201-376-6070
IJ Research, Santa Ana, CA, 714-253-8522
Advanced Packaging Concepts, San Diego, CA 619-450-1370
Mini-Systems, Inc., Plainville, MA 508-695-2000
Memory Stack:Irvine Sensors Corporation, Costa Mesa, CA 714-549-8211
Cubic Memory, Scotts Valley, CA 408-438-1887
Metal Deposition and Flip Chip Assembly:MCNC, Research Triangle Park, NC 919-248-1800
Flip Chip Technologies, Phoenix, AZ 602-431-6020
nChip, San Jose, CA 408-945-9992
The following two companies have been identified as possible sources of the final assembly for future builds for flight grade parts.
Final Product Source:nChip, San Jose, CA 408-945-9992
Austin Semiconductor, Austin, TX , 512-339-1188
Chip Supply, Orlando, FL 407-298-7100
Points of Contact:Bob Savage, Code 735, 286-6616
Jeannette Plante, Swales, 902-4310
M. Ann Darrin, Code 310, 286-6588