Known Good Die, MCM, Programmable Logic and Substrates

Fast Cycle Programmable High Density Electronics:
Known Good Die, Multi-Chip Modules,
Programmable Logic and Substrates

Richard Katz, NASA GSFC
Jeannette Plante, Swales Aerospace

Abstract

The use of programmable logic and substrates combined with other advanced packaging techniques, is critical to smaller and lighter space flight electronic assemblies. Temporary and semi-permanent die carriers have been found to be critical tools for reducing the reliability risks associated with using complex die such as gate arrays. The results of a NASA GSFC evaluation of these carriers will show technical viability of these fixtures for use by designers of chip-on-board and multi-chip module electronic assemblies for high-rel systems.

1.0 Introduction:

It is critical to the space industry to move its electronics into smaller and more flexible form factors to counter increasingly smaller budgets and tighter schedules. An array of leading edge technologies exist that can help move NASA hardware to this end (Figure 1). The work described here focuses on three of these major technology areas: Known Good Die (KGD), programmable logic and programmable substrates. Along with integration techniques, these are the main vehicles which will make future flight electronics highly design flexible, low in cost, quick to process and orders of magnitudes smaller than their existing counterparts.

KGD, programmable logic, and programmable substrates will enable designers to replace individually packaged logic parts with single die and allow quick-turn prototyping with hardware and tools that are rugged enough and flexible enough to be exposed to qualification testing. By using the programmable technologies directly in flight hardware, an extremely short path can been established between conceptual and flight ready electronics. With existing and upcoming on-site assembly capabilities quick production cycles can be realized.

Figure 1. Technology Paths to Miniaturized High Reliability Electronics

2.0 Background:

The electronics industry is continuously pressured to increase functionality and to extend beyond the engineering limits of existing technologies to reduce footprint and power requirements. As a result, state of the art technological advances are being achieved at every level from the part package and assembly down to semiconductor material compositions and designs. Over the last ten years, two of these technologies have been highly successful in miniaturizing flight hardware: Very large scale integrated circuits (VLSI) - massively complex standard circuits, such as microprocessors, on one chip - and multi-chip modules (MCM’s) - many die contained in one package. Now, bare die mounted directly to circuit cards, chip-on-board (COB), is being used to miniaturize even more.

2.1 Known Good Die

A rule of thumb in MCM manufacturing is that if more than five dice of any given type, or devices with more than 200 bonds, are included in a single package, they must be KGD. This evolved from industry’s experience with the high cost of rework at the die level compared to the cost of replacing failed, packaged parts at the board level. Cost impacts are likewise more severe when the user encounters a failed MCM, as opposed the cost of replacing a individually packaged integrated circuit (IC). To avoid this cost risk, MCM production strategies are evolving, balancing rework costs with the cost of procuring guaranteed KGD.

KGD generically refers to a die level product provided by an IC manufacturer to an MCM manufacturer, carrying with it some level of guaranteed reliability. Approaches for achieving KGD vary by device type and by die manufacturer. JPL issued a study on industry practices and KGD in April of 1994 and included descriptions of the main tools used for establishing KGD: wafer level electrical testing, including techniques that build in test structures, and die level testing using temporary, semi-permanent and permanent packaging techniques. Though the techniques and vehicles for establishing a product as KGD are well understood, die manufacturers have placed little emphasis on establishing KGD programs since the die market represents less than 1% of their total IC sales [1]. The more comprehensive programs tend to have very high non-recurring engineering (NRE) costs, on a device type basis, and have limited useful lifetimes given the rapidly changing nature of semiconductor technology. It is incumbent then, on the user, to identify the technologies for which the use of KGD is critical and how best to invest the associated cost. This study has identified a complex device with a large number of pin-outs (175) that can be almost universally applied to all NASA programs: the field programmable gate array (FPGA).

2.2 Programmable Logic Circuits

FPGA’s can be used to scale down board and hybrid package sizes by orders of magnitude. FPGA’s can be programmed to take the place of most logic circuits. This leaves the microprocessor and memory chips as the majority type of individual parts left in the MCM package, making the MCM small and more straightforward to assemble. The advantages of using FPGA’s can be canceled by lead time problems and high rework costs if failures are encountered. Good KGD plans and tools remove a lot of this risk.

The first electrical design for programmable logic used metal based fuses. Programming consisted of electrically "blowing" selected fuses. This technology was superseded by a dielectric "antifuse" design which uses the programming voltage to create a conduction path, instead of an electrical open, at selected connection points. The dielectric antifuse approach solved problems that had been encountered with metal fuses reconnecting over time, with leakage current. Dielectric antifuse technology requires gate layout in parallel channels across the die, which alternate with the channels used by the metal routing paths and antifuse connections. A new technology uses an amorphous silicon material sandwiched between the metal routing paths which can be positioned on top of the gate structure [4,5]. This architecture reclaims die real estate which had been reserved for the antifuses alone in the dielectric antifuse technology, making much higher gate densities achievable. Table 1 compares the dielectric antifuse and amorphous silicon technologies.

Table 1. Antifuse Technologies

2.3 Programmable Substrate

The key to quick prototyping using FPGA’s and MCM’s is a field programmable substrate. Until this technology was available, long lead times were experienced waiting for the design and manufacture of the metallized substrates which electrically marry the chip to the package. Though programmable substrates are now available from Pico Systems, they have only recently been investigated for use in flight hardware. A 1996 DDF project is currently investigating this technology. A good application for this technology is integration with the high density programmable logic or memory devices to provide very small, highly flexible, field programmable logic circuitry that can be universally applied in NASA hardware.

3.0 Goals and Objectives

A task was established in this year to reduce the packaging size of electronic circuitry by facilitating the use of high pin count very large scale integrated (VLSI) circuits and programmable substrates while maintaining space grade level testing and reliability standards. FPGA’s were suggested as a test vehicle due to their wide applicability throughout space flight hardware. By using fixturing for dice that is compatible with existing test, evaluation and burn-in infrastructure, these complex devices can be made available to NASA designers as KGD. Combining die handling tools and programmable substrates with existing resources at Goddard Space Flight Center (GSFC) for rapid prototyping of circuits using FPGA’s, a concept-to-flight path can be established for this technology.

4.0 Two Carrier Technologies Examined

An extensive industry survey resulted in the selection of the Die Mate as the optimum die carrier technology for evaluation. This product is highly mature from a commercial production standpoint and extends the least amount of physical damage to the die surface. The Snapstrate has also been identified as a promising approach and has been investigated as well. The Die Mate is a removable package and the Snapstrate is a semi-permanent package. Both enable full functional testing and burn-in of devices before they are assembled in flight hardware. Die Mate, a product of Texas Instruments (TI) and MicroModule Systems (MMS), was used in production by Intel for their 486 microprocessor and by Cray Research for a complex die with over 900 area array connections [2]. The Die Mate provides a very rugged package that can be used over and over again, for a given die type. Snapstrate is an approach developed by Lockheed-Martin (Orlando, FL) which can be much cheaper and faster to process than the Die Mate. The Snapstrate employs wire bonding from the die to a substrate carrier which, after full screening, can be mounted and wire bonded to the MCM package substrate. This approach has a lower associated NRE but results in an ultimately larger device footprint.

The Die Mate’s (Figure 2) mechanical design provides a special alignment border, called the fence, which accurately positions the bare die in the carrier [2,3]. This feature allows manual or automated handling of the die. Top and bottom package layers provide contamination control and mechanical support for the die. The package lid also provides heat sinking to avoid overstressing the device due to self-heating during burn-in. The die lies in the carrier faced down such that the bond pads make contact with a resilient metallized membrane. The membrane is thick film on polymer technology and can be multilayered for bias, signal and ground paths. These circuit paths lead out to an internal package bond which connects with the external socket pins. The Die Mate can be exposed to full temperature and electrical testing exactly as is done with standard military grade packaged parts.

When fully assembled, the membrane-to-die contact points actually pierce the resident die pad oxide making good connection with the pad metallization. Perimeter or array connection configurations can be used. MMS specifies reuse of the membrane 1000 times and reuse of the socket 10,000 times. Test signal speeds of over 250MHz with over 180 simultaneously switching signals are specified by MMS. This type of rugged, high performance, electrical connection, without damage to the die, is not achievable with other KDG carriers and or traditional microprobe techniques.

Figure 2. Die Mate

The Snapstrate approach uses a ceramic substrate with circuit metallization designed for the die being tested. This semi-permanent carrier uses traditional die mounting techniques and materials including epoxy and wire bonding. This substrate, with the die attached, can be exposed to full electrical and thermal testing (Figure 3). Once the die is fully screened, the portion of the substrate to which the die is bonded, including some small additional area beyond a second set of substrate bond pads, is broken away leaving an assembly, slightly larger than the die, that can be epoxy and wire bonded to an MCM substrate (Figure 4). Though the Snapstrate is not a reusable tool, it is significantly cheaper and more easily fabricated than the Die Mate.

Figure 3. Snapstrate

Figure 4. Snapstrate Final Footprint: 0.5" Square

Coordination with other users of KGD have brought attention to a new carrier approach. Loranger International has begun producing a chip scale package carrier and socket pair which uses micro ball grid array connections in the carrier and land grid array contacts on the socket. The design has the potential for providing NASA with an additional low cost, fast turn around, temporary KGD carrier. Two other local KGD user organizations have expressed an interest in working together, with NASA, to evaluate this technology: NSA (Ft. Meade) and Northrup-Grumman (Baltimore).

5.0 Work To Date

Due to agency-wide interest in and need for these technologies, JPL contributed funding from their NASA Headquarters sponsored Known Good Die program, toward completion of the stated goals.

To date, the work has involved working with the commercial partners to establish the preliminary design of the Die Mate and Snapstrate for the FPGA die. In order to avoid test difficulties encountered in the past, when third party manufacturers tried to repackage this complex part, NASA GSFC and Actel, the die manufacturer, put together and signed a memorandum of understanding regarding the purchase, use and testing of the die. This agreement was critical to this and future Actel die procurements by NASA.

Inquiries were made throughout the industry to get field experience histories for the Die Mate and other similar technologies. The advantages found for the Die Mate were: low damage to die pads, no post processing by the die manufacturer, good contamination control, its reusable fixturing, direct integration with existing test equipment and no increase in final device footprint.

Once the agreements and plans were established, design work began at GSFC for the Die Mate. NASA GSFC worked extensively with Actel to supply MMS accurate databases for die bond pad locations and geometry’s, chip geometry and critical electrical circuit paths. This information is critical for successful Die Mate design because the precise, non-damaging, die interconnection relies on precise three dimensional tolerances. Signal and bias lines have been isolated to prevent cross-talk and to reduce noise thus enabling high speed electrical testing.

At GSFC, burn-in boards, wiring harnesses and single event effect radiation testing fixtures were designed and built. A socket adapter was designed and specified to integrate the 280 pin Die Mate footprint with existing test circuits designed for a 172 pin grid array. Ironwood was contracted to build these adapters to the GSFC specifications.

An order was established through NASA GSFC purchasing for 45 Die Mates (280 leads), 45 membranes designed for the Actel A1280XL and 25 test sockets (for test board integration). Delivery is expected four months following contract award. An order has also been placed for the Actel A1280XL die.

Under sponsorship by Code 310, an order was placed with Lockheed-Martin for 30 Snapstrate carriers and associated processing tools. The design is in review and once it has been approved by NASA GSFC and Actel, the die will be supplied to Lockheed-Martin for mounting on the Snapstrate carriers. Testing and evaluation will be accomplished by Actel and NASA GSFC.

Upon receipt of these materials, some initial tests will be run on the die, using both the Die Mate and Snapstrate configurations. The devices will then be programmed and retested. Following successful completion of programming, a rigorous burn-in test, followed by a functionality check will be performed. Finally, the die will be removed from the Die Mate and evaluated for contamination, bond pad damage, wire bondability and other related mechanical and material characteristics to verify that the Die Mate did not introduce any physical defects to the die that could cause failure at the MCM substrate level.

6.0 Planned Follow-on Work on KGD, Programmable Logic and Programmable Substrates

The work discussed above will provide a great deal of experience with handling and testing die and will provide much needed insight into the detailed investigations required to design die carriers. Given the development of this new resource, it is advantageous to GSFC to continue this work with similar emerging technologies such as the Loranger die carrier, UTMC’s amorphous silicon technology and Pico’s programmable substrate. By following this path for providing electronics designers with tools which streamline prototyping and testing functions, NASA is able to take advantage of and build upon commercially available, leading edge technologies that miniaturize electronics.

7.0 Resources

Brutacao, James, Known Good Die: Facilitating Multi-Chip Modules, JPL, April 29, 1994.
Green, Howard; Burger, Richard, Press Release, MicroModule Systems.
Agahdel, Fariborz; Teoh, Hongbee; Rizzo, Salvatore; Roebuck, Randal; Known Good Die Carrier Reliability Evaluation, MicroModule Systems and Texas Instruments.
Actel and the Antifuse, Actel, http://www.actel.com/marcom/bckgrnd/antifuse.html, August 1996.
Wong, Richard J.; Gordon, Kathryn E.; Chan, Andrew K., Time Dependent Reliability of the Programmed Metal Electrode Antifuse, Quicklogic Corp., IEEE International Reliability Physics Symposium, May 1996.