3.1 Device Hours Summary
Table 3 below summarizes the total device-hours at each temperature for this evaluation. The test was not run continuously. The last increment of 85 C testing was completed on 12/18/96.| 25 C | 85 C | 125 C |
|---|---|---|
| 8256 | 10176 | 6576 |
The final 2256 device hours at 85 C utilized the 25 C PEC circuits. These devices were stimulated with 20 mA, 100 mA and 300 mA load circuits. This provided a step-stress evaluation of the circuit.
3.2 Icc Antifuse Stress Summary
Both of the 125 C parts exhibited failures. S/N 2 (Icc #1) at 125 C shows an anomaly at about 800 hours which is manifested as an Icc drop. This is displayed in figure 9e. It failed completely after 1464 hours. The 20 mA current line dropped to near zero and simply exhibited spikes as the device toggled through enable and disable cycles. The setup was left undisturbed to allow the other device to continue. S/N 3 (Icc #2) had a failure on the 100 mA current line. The 100 mA circuit was not biased at 125 C and was not monitored. Figures 8a-f are the final current plots for all 6 devices and all three current lines. This data was taken at 25 C except for 8a and b which were the last +85 C plots before the chamber was shut down. There is no trend data available for the unbiased lines. Both the 85 C and 25 C PEC MCMs appear normal with little variation from the original baseline.A review of the datalogger data reveals that each circuit initially undergoes an increase current over the first 400 hours of the test and then a gradual decrease in current over time. This data is in figures 9a-f. This response is complex, non-linear and probably represents multiple phenomena. One can speculate over a number of plausible scenarios. These scenarios may include a period of decreasing resistance due to migration of metal into the antifuse-metal interfaces or an initial change in the morphology of the metal-silicon programmed antifuses possibly induced by thermoelectric stress at the start of the test. After an initial period, the condition of the programmed antifuses either "stabilizes" or an extended period of decreasing Icc current is measured due to metallization wearout at points of highest current density which becomes the dominant phenomena. The initial increase in current is greatest in the 25 C devices, which also have the highest current levels.
Other scenarios are also possible. It is very possible that the trends in the data are due to the ACT540 implementation in an unconventional manner by tying the outputs together and switching them simultaneously repeatedly to provide high peak pulse currents. It is also possible that the +125 C failure is due to the ACT540. Otherwise it would be hard to explain why the 20 mA chains failed but not the 100 mA chains and why all four 20 mA chains failed within the same module ‘two by two’. Furthermore, the spikes can not be caused by a failed antifuse. Much of the evidence points at the ACT540 dice. Unfortunately, the datalogged data does not isolate each of the individual circuits within the PEC MCM. Additional analysis is required in this area. Table 4 provides a summary of statistics for the 20 mA, 100 mA and 300 mA Icc stressed circuits. Obvious data errors from the data logger were removed.
Another unexplained artifact from the test are the current spikes that appear on the +85 C and +125 C units. These can be clearly seen in the Appendix A current plots. These spikes and their effect on the antifuses will be investigated further via circuit modeling.
Figure 8a
Figure 8b
Figure 8c
1/9/97
Figure 8d
1/9/97
Figure 8e
1/9/97
Figure 8f
1/9/97
Figure 9a
Figure 9b
Figure 9c
Figure 9d
Figure 9e
Figure 9f
Table 4
Summary Statistics for Icc stressed antifuse lines